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LTM4603HV
PI FU CTIO S
(See Package Description for Pin Assignment)
MARG0 (Pin C12): This pin is the LSB logic input for the
margining function. Together with the MARG1 pin will
determine if margin high, margin low or no margin state
is applied. The pin has an internal pull-down resistor of
50k. See Applications Information.
MARG1 (Pin D12): This pin is the MSB logic input for the
margining function. Together with the MARG0 pin will
determine if margin high, margin low or no margin state
is applied. The pin has an internal pull-down resistor of
50k. See Applications Information.
SGND (Pin H12): Signal Ground. This pin connects to
PGND at output capacitor point.
COMP (Pin A11): Current Control Threshold and Error
Ampli?er Compensation Point. The current comparator
threshold increases with this control voltage. The voltage
SI PLIFIED BLOCK DIAGRA
ranges from 0V to 2.4V with 0.7V corresponding to zero
sense voltage (zero current).
PGOOD (Pin G12): Output Voltage Power Good Indicator.
Open-drain logic output that is pulled to ground when the
output voltage is not within ±10% of the regulation point,
after a 25μs power bad mask timer expires.
RUN (Pin A10): Run Control Pin. A voltage above 1.9V
will turn on the module, and when below 1.9V, will turn
off the module. A programmable UVLO function can be
accomplished with a resistor from V IN to this pin that has
a 5.1V zener to ground. Maximum pin voltage is 5V.
V OUT_LCL (Pin L12): V OUT connects directly to this pin to
bypass the remote sense ampli?er, or DIFFV OUT connects
to this pin when remote sense ampli?er is used.
V OUT_LCL
>2V = ON
<0.9V = OFF
1M
V OUT
MAX = 5V
RUN
PGOOD
COMP
5.1V
ZENER
1.5 μ F
+
C IN
V IN
4.5V TO 28V
60.4k
INTERNAL
COMP
SGND
MARG1
MARG0
POWER CONTROL
Q1
22 μ F
V OUT
2.5V
6A
R FB
19.1k
V FB
f SET
50k
50k
Q2
C OUT
+
MPGM
33.2k
PGND
C SS
TRACK/SS
PLLIN
INTV CC
DRV CC
4.7 μ F
50k
10k
INTV CC
10k
10k
10k
V OSNS–
V OSNS+
DIFFV OUT
4603HV F01
Figure 1. Simpli?ed LTM4603HV Block Diagram
4603hvf
8
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